Composition du jury :

François Rieutord CEA-INAC, Grenoble Rapporteur

Pierre Muller CiNam, Marseille Rapporteur

Daniel Alquier LMP, Tours Examinateur

Vincent Paillard CNRS-CEMES, Toulouse Examinateur

Marc Respaud LPCNO-INSA, Toulouse Examinateur

Didier Dutartre ST Microelectronics, Crolles Examinateur

Alain Claverie CNRS-CEMES, Toulouse Directeur de thèse

Oleg Kononchuk SOITEC, Bernin Co-directeur de thèse

Abstract :

New generations of CMOS transistors will be fabricated on Fully Depleted Silicon-On-Insulator (FD-SOI) wafers. A FD-SOI wafer consists of an ultrathin (typically of the order of 10 nm thin) top silicon layer sitting on top of a buried oxide (BOx) layer itself on top of a thick (500 µm) Si handle wafer. As final transistor characteristics dramatically fluctuate with thickness variations of the top layer, the capability of assessing and mastering thickness uniformity over a large spatial bandwidth (from transistor to wafer scales, 10 nm - 300 mm), has become the real challenge for the CMOS technology to overcome. In this work, we first propose a multi-scale metrology method, based on the treatment of data recorded from several experimental techniques and using Power Spectral Density (PSD) functions, to describe both roughness and thickness variations of thin layers over the bandwidth of interest. Furthermore, using these methods, we investigate the impact of some of the elementary technological process steps involved in the fabrication of the FD-SOI layers using the Smart CutTM technology, on the resulting thickness uniformity characteristics. The spectral analysis of thickness variations provides a spectral foot-print of these processes. Finally, we investigate the underlying physical mechanisms involved in the surface smoothening of Si layers by thermal annealing. We develop a statistic model describing surface self-diffusion allowing us to predict the thermal evolution of the topography of Si surfaces during thermal annealing.